This application is based upon and claims priority of Japanese Patent Application No. 2001-216506, filed on Jul. 17, 2001, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a test equipment and, more particularly, to a test equipment which is expected to rapidly complete its task and to check the quality of a semiconductor.
2. Description of the Related Art
The quality of a semiconductor integrated circuit is conventionally checked by utilizing a tester for large-scale semiconductor integrated circuit. As one item in the quality check, it is well-known to carry out a speed-check.
If a semiconductor circuit to be examined is expected to function at high speed over a permissible range of the LSI(Large-scale Integration) tester, the examination can not be attained. An examination equipment shown in FIG. 11 is conventionally used in the art.
A conventional art for accomplishing a high-speed test of an LSI is shown in FIG. 11. The LSI under test (DUT: Device under test) 1102 is connected onto an evaluation board[FT(Final-test) board] 1101. The LSI 1102 comprises a circuit 1122 under test which works as an input section, a determination circuit 1121, a test circuit 1111, and a circuit 1112 under test which works as an output section. The circuit 1122 under test is composed of a terminating resistance 1123, an input buffer 1124, and a processing circuit 1125. The circuit 1112 under test is composed of a terminating resistance 1113, a processing circuit 1115, and an output buffer 1114. The output of the output buffer 1114 and the input of the input buffer 1124 each are connected on the evaluation board 1101. The output of the output buffer 1114 and the input of the input buffer 1124 are connected with the terminating resistances 1113 and 1123, respectively.
The LSI 1102 is capable of outputting high-speed signals from the output buffer 1114 and inputting the high-speed signals into the input buffer 1124. In this high-speed test, a high-speed test signal is outputted from this output buffer 1114 to thereby determine by inputting the signal into the input buffer 1124.
Specifically, the test circuit 1111 outputs the test signal to the circuit 1112 under test. The circuit 1112 under test executes its prescribed process for this test signal and then outputs the result to the circuit 1122 under test. The circuit 1122 under test executes its prescribed process for that inputted signal and then outputs the result to the determination circuit 1121. The determination circuit 1121 is therefore determine the quality of the circuits 1112 and 1122 by evaluating the signal inputted therein.
The conventional LSI test involves the following problems.
(1) The exclusive evaluation board 1101 is inevitable in order to connect the circuit 1112 under test of the output section with the circuit 1122 under test of the input section.
(2) Two tests are necessary, one being a standard test(hereinafter referred to xe2x80x9cLow-speed testxe2x80x9d) on one board by using the tester and the other being the high-speed test with the other board 1101.
(3) When the number of the circuit 1112 under test of the output section and that of the circuit 1122 under test of the input section are not agreed, some circuits under test are left behind the test.
(4) Since the LSI 1102 under test is connected to the evaluation board 1101 via a socket, the impedance becomes large. The circuits 1112, 1122 under test tend to be harmed by noise to thereby invite errors.
An object of the present invention is to save time for the test by exploiting a single evaluation board which is capable of completing both of the low-speed test and the high-speed test for a circuit under test.
Another object of the present invention is to perform a test for any circuit even when the number the circuit under test of the input section and that of the circuit under test of the output section are not agreed.
Still another object of the present invention is to prevent a noise generation throughout the test.
A preferable aspect of the present invention is provided as a test equipment which comprises: a circuit under test including a first terminating resistance connected to a first terminal; a first test circuit: including a second terminal connected to the first terminal of said circuit under test and excluding a terminating resistance connected to the second terminal for outputting a high-speed test signal to said circuit under test via the second terminal; a tester including a third terminal connected to the second terminal of said first test circuit, the third terminal being connected to the second terminating resistance when said first test circuit outputs the high-speed test signal, or the third terminal being connected to a second test circuit for outputting a low-speed test signal to said circuit under test via the third terminal when said first test circuit does not output the high-speed test signal; and a determination circuit for evaluating the outputted signal of said circuit under test. In this structure, a wiring between the first terminating resistance, the first terminal, the second terminal, the third terminal, and the second terminating resistance is joined in this serial order, when said tester connects the second terminating resistance to the third terminal.
Accordingly, the first test circuit outputs the high-speed test signal to the circuit under test, while the second circuit under test outputs the low-speed test signal to the circuit under test. It is therefore achieved to carry out both of the high-speed and low-speed tests on the single evaluation board to thereby save time for the test.
As the circuit under test and the first test circuit each are independent semiconductor chips, all the circuits under test can be examined well even when the numbers are different between the circuit under test as the input section and the circuit under test as the output section.
The semiconductor chip of the circuit under test is connected to the evaluation board via the socket, and the semiconductor chip of the first test circuit is directly connected to the same evaluation board to thereby prevent a noise generation throughout the test and an error state of the equipment due to the noise.